ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

Autores

  • Arash Rezapour Department of Electronic, Arak Branch, Islamic Azad University, Arak, Iran
  • Mohammad Bagher Tavakoli Department of Electronic, Arak Branch, Islamic Azad University, Arak, Iran
  • Farbod Setoudeh Department of Electronic, Arak University of Technology, Arak, Iran

DOI:

https://doi.org/10.22478/ufpb.2179-7137.2019v8n3.47576

Palavras-chave:

Analog to Digital Pipeline, Comparator, Amplifiers, Buffer

Resumo

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

Downloads

Não há dados estatísticos.

Referências

Rezapour, A., Tavakoli, M-B., Setoudeh, F. A new Approach for 10-bit Pipeline analog-to-digital convertor design based on 0.18µm CMOS Technology. AEU-International Journal of Electronics and Communications, 99 (2019) 299–314.

Lv, J., Que, L., Wei, L., Meng, Z., & Zhou, Y. A low power and small area digital self-calibration technique for pipeline ADC. AEU-International Journal of Electronics and Communications 83 (2018): 52-57.

Fatemi-Behbahani, E., Farshidi, E., & Ansari-Asl, K. (2016). Analysis of chaotic behavior in pipelined analog to digital convertor s. AEU-International Journal of Electronics and Communications, 70(3), 301-310.

Yoshioka, Kentaro, Tetsuro Itakura, and Masanori Furuta. A/D convertor circuit, pipeline A/D convertor, and wireless communication device. U.S. Patent No. 9,608,657. 28 Mar. 2017.

‏

Steensgaard-Madsen, J. (2016). U.S. Patent No. 9,331,709. Washington, DC: U.S. Patent and Trademark Office.‏

Correia, A. P. P., Barquinha, P. M. C., & da Palma Goes, J. C. (2016). Analog-to-Digital Convertor s. In A Second-Order ΣΔ ADC Using Sputtered IGZO TFTs (pp. 49-56). Springer, Cham.‏

Cárdenas-Olaya, A. C., Rubiola, E., Friedt, J. M., Bourgeois, P. Y., Ortolano, M., Micalizio, S., & Calosso, C. E. (2017). Noise characterization of analog to digital convertor s for amplitude and phase noise measurements. Review of Scientific Instruments, 88(6), 065108.‏

Khorami, A., & Sharifkhani, M. (2016). High-speed low-power comparator for analog to digital convertor s. AEU-International Journal of Electronics and Communications, 70(7), 886-894.‏

de Aguilar, J. D., Salinas, J. R., Lapuh, R., Méndez, A., Lagos, F. G., & Sanmamed, Y. A. (2016, July). Characterization of the amplitude frequency response of analog-to-digital convertor s. In Precision Electromagnetic Measurements (CPEM 2016), 2016 Conference on (pp. 1-2). IEEE.‏

Prakash, A. J., Jose, B. R., Mathew, J., & Jose, B. A. (2018). A Differential Quantizer-Based Error Feedback Modulator for Analog-to-Digital Convertor s. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(1), 21-25.‏

Kiran, K. Ravi, et al. A 5-bit, 0.08 mm 2 area flash analog to digital convertor implemented on cadence virtuoso 180nm."Emerging Trends in Engineering, Technology and Science (ICETETS), International Conference on. IEEE, 2016.‏

Khalapure, S., Siddharth, R. K., & Vasantha, M. H. (2017, July). Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. In VLSI (ISVLSI), 2017 IEEE Computer Society Annual Symposium on (pp. 585-588). IEEE.‏

Liu, D., He, L., Lin, F., Li, T., & Chou, Y. K. (2017). A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications. Journal of Circuits, Systems and Computers, 26(07), 1750118.‏

Sarkar, Sudipta, Yongda Cai, and Anubhav Adak. Two-Step Residue Transfer Technique for High-Speed Pipeline A/Ds. VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017 30th International Conference on. IEEE, 2017.‏.‏

Adimulam, M. K., Movva, K. K., & Srinivas, M. B. (2017, September). A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications. In System-on-Chip Conference (SOCC), 2017 30th IEEE International (pp. 45-50). IEEE.‏

Ozeki, Toshiaki, Junichi Naka, and M. I. K. I. Takuji. A/D convertor including multiple sub-A/D convertor s. U.S. Patent No. 9,559,711. 31 Jan. 2017.‏

Chun-Cheng Liu et al., A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure. IEEE Journal of Solid-State Circuits, Vol. 45, NO. 4, April 2010 731.

Muratore, Dante Gabriel, et al. An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. European Solid-State Circuits Conference, ESSCIRC Conference 2016: 42nd. IEEE, 2016.‏

Mei, F., Shu, Y., & Yu, Y. A 10-bit 150MS/S SAR ADC with a novel capacitor switching scheme. In Computational Intelligence & Communication Technology (CICT), 2017 3rd International Conference on (pp. 1-6). IEEE (2017, February). ‏

Shu, Y. S., Kuo, L. T., & Lo, T. Y. (2018). A Hybrid Architecture for a Reconfigurable SAR ADC. In Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design (pp. 79-97). Springer, Cham.‏

Buchwald, A. High-speed time interleaved ADCs. IEEE Communications Magazine, 54(4), 71-77 (2016). ‏

Ali, A. M., Dinc, H., Bhoraskar, P., Dillon, C., Puckett, S., Gray, B... & Jeffries, B. (2014). A 14 Bit 1 GS/s RF sampling pipelined ADC with background calibration. IEEE Journal of Solid-State Circuits, 49(12), 2857-2867.‏

Huang, X., Fu, D., Hu, R., Pu, J., Shen, X., Li, J., & Li, L. (2015). A 14-b 500 MSPS Time-Interleaved Analog-to-Digital Convertor with Digital Background Calibration.‏

Boo, H. H., Boning, D. S., & Lee, H. S. (2015). A 12b 250 MS/s pipelined ADC with virtual ground reference buffers. IEEE Journal of Solid-State Circuits, 50(12), 2912-2921.‏

Wang, C., Wang, X., Ding, Y., Li, F., & Wang, Z. (2018, May). A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique. In Circuits and Systems (ISCAS), 2018 IEEE International Symposium on (pp. 1-5). IEEE.‏

Roy, S., & Banerjee, S. A 9-Bit 50 MSPS Quadrature Parallel Pipeline ADC for Communication Receiver Application. Journal of the Institution of Engineers (India): Series B, 1-14 (2018).

Li, Fei. "1.5 bit-per-stage 8-bit Pipelined CMOS A/D Convertor for Neuromophic Vision Processor." arXiv preprint arXiv:1701.08877 (2017).‏

Fan, Q., Chen, J., Wen, X., Feng, Y., Tang, Y., Zuo, Z. & Ye, J. (2017). A low-power 10-bit 250 MS/s dual-channel pipeline ADC in 0.18 μm CMOS. Journal of Instrumentation, 12(02), C02018.‏

SHA TAO, Power-Efficient Continuous-Time Incremental Sigma-Delta Analog-to-Digital Convertor s. Universitetsservice US AB, Sha Tao, May 2015.

Jayesh L.V yas, Simulation of 3 bit Flash ADC in 0.18µm Technology using NG SPICE Tool for High speed Application. IJSRD.International Journal for Scientific Researc, DevelopmentVol,1,Issue2,2013.

Andrew Masami Abo, Design for Reliability of Low-voltage, Switched-capacitor Circuits. Ph.D. thesis, University of California at Berkeley, 1999

Downloads

Publicado

2019-08-30

Como Citar

REZAPOUR, A.; TAVAKOLI, M. B.; SETOUDEH, F. ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER. Gênero & Direito, [S. l.], v. 8, n. 3, 2019. DOI: 10.22478/ufpb.2179-7137.2019v8n3.47576. Disponível em: https://periodicos.ufpb.br/ojs/index.php/ged/article/view/47576. Acesso em: 19 nov. 2024.

Edição

v. 8 n. 3 (2019)

Seção

Seção Livre